Low dielectric constant (low-k) materials are important for semiconductors as such materials allow a semiconductor device to run with less capacitance coupling or crosstalk and therefore less delay. A substantial amount of work has gone into the development of low-k materials by those skilled in the art so that such materials are compatible with semiconductor integrated circuit manufacturing processes and equipment and so that the materials still have the lowest dielectric constant value possible. A variety of low-k materials are known to those skilled in the art including spin on and chemical vapor deposition types of organic and inorganic materials. Fluorinated silicon oxide has a dielectric constant value of 3.6. For plasma enhanced chemical vapor deposition deposited low-k, Applied Materials' BLACK DIAMOND and Novellus' CORAL have dielectric constants of about 2.6-2.9. Spin-on low k materials such as Honeywell's HOSP and Dow's SILK, etc., typically have dielectric consant values of 2.5-2.9. AEROGEL has a dielectric constant below 2 but is very fragile due to the high void ratio so it does not have much practical use as of today. Because of their unique mechanical, chemical and etch properties, these new materials have added many new integration/process issues as compared to silicon dioxide based dielectrics.
The lowest possible dielectric constant value, by definition, is “one” which is associated with air or vacuum. Heretofore, integrated circuit manufacturing technology did not provide for a means of building such a device consistently with air or voids as the dielectric. To date, the integrated circuit manufacturing process needs to use physical, solid dielectric and conductive materials to build the final device.
Traditionally, semiconductor devices are made using the “subtraction” method. For example, first a metal layer is deposited. Certain portions of the metal layer are then removed by using a photoresist pattern and plasma etching to define metal lines. The dielectric (for example silicon dioxide) is then filled in between the metal lines using spin on glass or high-density plasma. The oxide surface is planarized using chemical mechanical planarization. This prepares the surface for the next layer.
Recent processes use chemical mechanical planarization and damascene techniques for both oxide and metal layers. Instead of metal etch, a dielectric is patterned with photoresist and etched to form holes and trenches. Metal is deposited (by sputtering or electroplating) into the holes and trenches to form the interconnection. Chemical mechanical planarization polishing is used to remove metal from the top of the dielectric layer. Then the surface is ready for the next dielectric deposition and subsequent repeated process steps.
Regardless of which way the metal is patterned, the device is finally capped with a layer of plasma enhanced chemical vapor deposition silicon nitride which is impermeable to moisture and which is commonly called passivation. Subsequent passivation etch will etch off (away) silicon nitride over the metal bond pads and expose the metal bond pads (typically aluminum or copper). Therefore, the wafer surface is sealed with silicon nitride and only the metal bonding pads are exposed. This guarantees the reliability of the device and that no external element can attack the encapsulated device. The device is then subsequently packaged and typically assembled onto circuit boards.
Air as the dielectric has previously been proposed. The Engel et al., U.S. Pat. No. 6,472,740, discloses covering a device using a mesh shaped disk. The device has air in between the metal lines of the disk. The mesh openings are then filled with an insulating material to form a cap. However, this method is most likely too cumbersome for use in high-volume production.
Fitch et al., U.S. Pat. No. 5,324,683, discloses a method for forming an air region or air bridge overlying a base layer. Air regions are formed overlying the base layer to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form any other micro-structures or micro-devices. Air regions are formed by either selectively removing a sacrificial spacer or by selectively removing a sacrificial layer. The air regions are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions may be formed under any pressure, gas concentration or process conditions. The air regions may be formed at any level within the integrated circuit.
Gnade et al., U.S. Pat. No. 5,750,415, discloses a method for forming air gaps between metal leads of a semiconductor device. A metal layer is deposited on the substrate. The metal layer is etched to form metal leads exposing portions of the substrate. A disposable liquid is deposited on the metal leads and the exposed portions of the substrate and a top portion of the disposable liquid is removed to lower the disposable liquid to at least the tops of the metal leads. A porous silica precursor film is deposited on the disposable liquid and over the tops of the leads. The porous silica precursor film is jelled to form a low-porosity silica film. The disposable liquid is removed from the low-porosity silica film to form air gaps between metal leads beneath the low-porosity silica film. The reference suggests that the process reportedly produces air gaps having a low dielectric constant and results in reduce capacitance between the metal leads and decreased power consumption. However, it is believed that this process is very different from current integrated circuit process techniques and would require substantial development and additional processing equipment to accomplish successfully.
Ghoshal, U.S. Pat. No. 6,204,165, discloses a method of fabricating an integrated circuit having air gaps between interconnect levels. An integrated circuit is partially fabricated and includes a top layer, interconnect structures having a cladding layer, dielectric layers and etch stop layer resistant to certain types of etchants. The top layer of the integrated circuit is etched with a second type of etchant. The dielectric layers are then etched with one of the first types of etchant until the etch stop layer is reached. Consequently, portions of the interconnect structures are exposed to create interconnect islands surrounded by a air. A cover is mechanically placed over the exposed interconnect islands to protect the integrated circuit from dust particles and other contaminants.
Dawson et al., U.S. Pat. No. 5,998,293, discloses an interconnect structure including pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by an air from one another. Air gaps are formed by dissolving a sacrificial dielectric, and the connectors are prevented from bending or warping in regions removed of sacrificial dielectric by anodizing the upper surfaces of each connector and side walls as well. The upper and side wall anodizing provides for a more rigid metal structure. However, this is a complicated process and the pillars utilize a substantial amount of valuable real estate on the semiconductor device.
Bartelink, U.S. Pat. No. 5,567,982, discloses an interconnect structure including conductive transmission line structure and a transmission line support structure. The support structure has a “railroad trestle-like” construction and provides a braced framework to support the transmission line which the author claims greatly reduces the effective dielectric constant. The trestle-like construction of the upper support includes a membrane-like structure and support base structure separated by column-like support members. Spacers between column-like support members form air pockets.
Natzle, U.S. Pat. No. 6,097,092, discloses a dielectric wiring structure and method of manufacturing. Successfully formed wiring layers synergistically combined with subsequent formed side wall support spanning two or more layers to form a self-supporting air dielectric interconnect matrix. Wires are supported by vertical nitride side walls which are, in turn, held in place and supported by the wires. After forming the complete wiring side wall structure, silicon dioxide between and under the wires is removed using gaseous hydrogen fluoride. The metal wires may be clad with nitride for short and oxidation protection. Because side walls are formed after wiring, with wiring at each level providing support, complex support alignment is reportedly not necessary. However, this process also takes up a substantial amount of valuable real estate in a semiconductor device and would have a higher dielectric constant value because of the support dielectric.
Potter et al., U.S. Pat. No. 4,899,439, discloses a high density electrical interconnect having a plurality of metal conductor supported from metal pillars which are electrically isolated from the ground planes by openings. The interconnect can be fabricated using temporary support dielectric, which may be removed after completion to provide an air dielectric or be replaced with a more suitable permanent dielectric. The removal of the temporary support allows the conductors to be coated with protective layers or with a layer of higher conductivity.
Leedy, U.S. Pat. No. 5,985,693, discloses a method for fabricating integrated circuits from flexible membranes formed of very thin low stress dielectric materials such as silicon dioxide and silicon nitride. The semiconductor devices are formed in the semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. An air bridge/tunnel structure where amorphous silica is used as a sacrificial layer is then selectively etched off.
Furthermore, some proposed to put down a lid on the device after etching off the dielectric. For high-volume production, this intricate capping technique will prove very difficult and the final reliability of the capped device will be hard to maintain consistently. It is believed that the above processes are not practical or complete.
The present invention provides improvements and/or alternatives to the prior art.